1. Field of the Invention
The present invention relates to clock delay circuitry incorporated into integrated circuits or the like and suitable for generating an internal clock signal in synchronization with an external clock signal applied thereto, and to oscillation circuitry, phase synchronization circuitry, and clock generating circuitry using the clock delay circuitry. More particularly, it relates to clock delay circuitry capable of setting and providing a time delay in steps of a specified time interval which cannot be restricted by a minimum of time delays provided by discrete circuit elements and transistors, and which is less than the minimum time delay, and to an oscillation circuit, a phase locked loop, and a clock generating circuit using the clock delay circuit.
2. Description of the Prior Art
Referring now to FIG. 11, there is illustrated a block diagram showing a clock generating circuit which can be contained on integrated circuits, as disclosed by "A Full-Digital PLL for LOW Voltage LSIs", TECHNICAL REPORT OF IEICE, Vol. 97, No. 106, pp. 29-36, June, 1997. In the figure, reference numeral 12 denotes an oscillation circuit for multiplying the frequency of a reference clock signal applied thereto and for furnishing a multiplied clock signal having the multiplied frequency, and 13 denotes a phase synchronization circuit for delaying the multiplied clock signal from the oscillation circuit 12 by a specified time interval and for furnishing a phase locked clock signal exactly in phase with the reference clock signal.
Reference numeral 14 denotes a loop inverter for inverting the multiplied clock signal, 16 denotes a first digital delay line (DLL) for delaying the output of the loop inverter 14 by a specified time interval defined by a delay setting signal applied thereto, and 51 denotes a delay adjustment circuit for delaying the output of the first DLL by a specified time interval defined by a delay setting signal applied thereto and for furnishing its output to the phase synchronization circuit 13 as the multiplied clock signal. Hereafter, the delay loop constructed of these circuits 14, 16, and 51 is referred to as multiplication delay loop.
Furthermore, reference numeral 19 denotes a first phase comparator which accepts the multiplied clock signal from the delay adjustment circuit 51 and the reference clock signal and then compares the phase of the reference clock signal with that of the multiplied clock signal so as to generate a first phase difference signal indicating the phase difference between the multiplied clock signal and the reference clock signal, and 20 denotes a first delay time setting circuit for generating and furnishing first delay setting signals each having a value that depends on the phase difference indicated by the first phase difference signal from the first phase comparator 19 to both the first DLL 16 and the delay adjustment circuit 51. The oscillation circuit 12 is thus comprised of the loop inverter 14, the first DDL 16, the delay adjustment circuit 51, the first phase comparator 19, and the first delay setting circuit 20.
Reference numeral 24 denotes a second digital delay line or DDL comprised of a plurality of delay elements in series, for delaying the multiplied clock signal from the delay adjustment circuit 51 by a specified time interval defined by a delay setting signal applied thereto and for generating a phase locked clock signal in phase with the reference clock signal, 26 denotes a second phase comparator which accepts the reference clock signal and the phase locked clock signal from the second DDL 24 and compares the phase of the reference clock signal and that of the phase locked clock signal so as to generate a second phase difference signal indicating the phase difference between these clock signals, and 27 denotes a second delay setting circuit for generating and furnishing a second delay setting signal having a value defined by the second phase difference signal from the second phase comparator 26 to the second DDL 24 to set the time delay to be provided by the second DDL 24. The phase synchronization circuit 13 is thus comprised of the second DDL 24, the second phase comparator 26, and the second delay setting circuit 27.
Referring next to FIG. 12, there is illustrated a schematic circuit diagram showing the structures of the delay adjustment circuit 51 and the first DDL 16. In the figure, reference numeral 52 denotes a DDL delay element which constructs part of the first DDL 16, 53 denotes an delay adjustment element which provides the same time delay as each of the plurality of delay elements 52, and 54 denotes an output selector which accepts both the output of the first DDL 16 and the output of the delay adjustment element 53 and then selects and furnishes one of them according to a switching signal applied thereto. Like the first DDL 16, the second DDL 24 includes a plurality of DDL delay elements 52 in series.
In operation, when the loop inverter 14 receives a falling edge of the multiplied clock signal from the delay adjustment circuit 51, the delay adjustment circuit 51 will furnish a rising edge of the multiplied clock signal after the expiration of a predetermined time interval. Similarly, when the loop inverter 14 receives a rising edge of the multiplied clock signal from the delay adjustment circuit 51, the delay adjustment circuit 51 will furnish a falling edge of the multiplied clock signal after the expiration of a predetermined time interval. The multiplied clock signal generated by the multiplication delay loop, which is constructed of the loop inverter 14, the first DDL 16, and the delay adjustment circuit 51, is thus a clock signal in which a transition from HIGH to LOW or from LOW to HIGH is repeated at established intervals having the same length as the time delay produced by the multiplication delay loop, with the result that the multiplied clock signal from the delay adjustment circuit 51 has a period two times as long as the time delay provided by the multiplication delay loop.
When the oscillation circuit 12 receives the reference clock signal while the multiplication delay loop, which is constructed of the loop inverter 14, the first DDL 16, and the delay adjustment circuit 51, operates in this manner, the first phase comparator 19 compares the phase of the reference clock signal with that of the multiplied clock signal from the delay adjustment circuit 51 and then generates a first phase difference signal indicating the phase difference between these signals. The first delay setting circuit 20 then generates first delay setting signals for setting the respective time delays produced by the first DDL 16 and the delay adjustment circuit 51 so as to reduce the phase difference.
Referring next to FIG. 13, there is illustrated a timing diagram showing an example of the operation of the prior art oscillation circuit 12. In the example shown in FIG. 13, the frequency of the multiplied clock signal is set to be four times as large as that of the reference clock signal. As shown in FIG. 13, a switching signal for causing the output selector 54 to switch the selection from the output of the first DDL 16 to the output of the delay adjustment element 53 is applied to the output selector 54 of the delay adjustment circuit 51 after the expiration of a three quarters part of the pulse duration of the reference clock signal since the rising edge of the reference clock signal. As a result, the time delay caused by the multiplication delay loop is changed to {(n+1).times..DELTA.d}, where .DELTA.d is the time delay provided by either one of each delay element 52 and the delay adjustment element 53, and n.times..DELTA.d is the immediately previous time delay caused by the multiplication delay loop.
As previously explained, the prior art oscillation circuit 12 can generate a multiplied clock signal having a frequency four times as large as that of a reference clock signal applied thereto by providing a delay adjustment circuit including a delay adjustment element 53 producing the same time delay as caused by each DDL delay element 52, and switching the selection by the selector 54 of the delay adjustment circuit 51 from the output of a first DDL 16 including a plurality of DDL delay elements 52 to the output of the delay adjustment element 53 within one period of the reference clock signal since the rising edge of the reference clock signal.
When the phase synchronization circuit 13 then receives the multiplied clock signal from the oscillation circuit 12, the second DDL 24 delays the multiplied clock signal by a specified time interval and the second phase comparator 26 then compares the phase of the multiplied clock signal delayed by the second DDL with that of the reference clock signal so as to generate a second phase difference signal having a value corresponding to the difference between the phases of the multiplied clock signal delayed and the reference clock signal. The second delay time setting circuit 27 then sets the time delay to be caused by the second DDL 24 so as to reduce the phase difference indicated by the phase difference signal from the second phase comparator 26. Thus the phase synchronization circuit 13 generates a phase locked clock signal in phase with the reference clock signal finally.
As previously mentioned, the prior art clock generating circuit can generate a multiplied clock signal having a frequency four times as large as that of a reference clock signal by means of the oscillation circuit 12, and make the multiplied clock signal in phase with the reference clock signal or anther clock signal associated with the reference clock signal by means of the phase synchronization circuit 13, so that the prior art clock generating circuit can generate a phase clocked clock signal having a frequency four times as large as that of the reference clock signal and synchronized with the reference clock signal or another clock signal. Referring next to FIG. 14, there is illustrated a timing diagram showing the mutual timing among multiplied and phase locked clock signals generated by the prior art clock generating circuit, and a reference clock signal.
Providing the delay adjustment circuit 51 and switching the selection by the delay adjustment circuit 51 from the output of the first DDL 16 to the output of the delay adjustment element 53 within one period of the reference clock signal since the rising edge of the reference clock signal, the multiplied clock signal can be finely synchronized with the reference clock signal compared with a prior art clock generating circuit in which where the time delay to be provided by the delay loop is adjusted by using only the first DDL 16. For example, when multiplying the frequency of the reference clock signal by 4, the synchronization of the multiplied clock signal must be done in delay steps of (4.times.2.times..DELTA.d=8.times..DELTA.d), where the time delay caused by each delay element 52 is .DELTA.d and the time delay caused by the delay adjustment element 53 is also .DELTA.d, in case that only the first DDL 16 is used for the delay adjustment. On the contrary, in case that the delay adjustment by the delay adjustment circuit 51 is combined with that by the first DDL 16, the synchronization of the multiplied clock signal can be done by adjusting the time delay produced by the multiplication delay loop in delay steps of .DELTA.d.
In such the prior art clock generating circuit so constructed, it is required to cause the delay adjustment circuit 51 to switch the selection within the time delay caused by the multiplication delay loop for the synchronization of the multiplied clock signal with the reference clock signal by means of the delay adjustment circuit 51, and it is therefore to speed up the whole of switching control circuitry, which includes such as the first delay time setting circuit 20, for controlling the delay adjustment circuit 51. In other words, the operating speed of the whole of switching control circuitry limits the minimum delay caused by the multiplication delay loop. This limitation further limits the multiplication factor provided by the multiplication delay loop.
In addition, since the delay adjustment circuit 51 is caused to change the output selection within the total time delay caused by the first DDL 16 and the delay adjustment circuit 51 of the multiplication delay loop for the synchronization of the multiplied clock signal with the reference clock signal, the pulse duration of the multiplied clock signal is varied by the adjustable delay time of .DELTA.d by the delay adjustment circuit 51, that is, the period of the multiplied clock signal is varied by (2.times..DELTA.d), resulting in a very large amount of jitter in the multiplied clock signal. A similar problem is caused when applying such the delay adjustment circuit 51 to the phase synchronization circuit 13.
To solve the above problem, a measure can be taken for adjusting the time delay by using a phase-locked loop or PLL as disclosed in "A 1V DSP for Wireless Communication", Wai Lee et al., ISSCC97, Digest of Technical Papers, pp. 92-93, issued on Feb. 6, 1997. Referring next to FIG. 15, there is illustrated a block diagram showing a phase-locked loop as disclosed in the reference mentioned above. In the figure, reference numeral 55 denotes a NAND gate which accepts an enable signal for controlling the operation of the NAND gate and its output fed back thereinto, 56 denotes a capacitor having a terminal connected to the output of the NAND gate 55, and 56 denotes an inverter connected to the other terminal of the corresponding capacitor 56, for holding the other terminal of the capacitor 56 at a HIGH or LOW logic level.
In operation, when the enable signal makes a LOW to HIGH transition while the output of the NAND gate 55 is held at a HIGH logic level, the output of the NAND gate 55 makes a HIGH to LOW transition. After that, the output of the NAND gate 55 will make a LOW to HIGH transition after the expiration of a specified time delay caused by itself. The NAND gate 55 thus repeats such transitions and generates a clock signal with a pulse duration having the same length as the time delay caused by the NAND gate 55.
After the outputs of the plurality of inverters 57 make a HIGH to LOW transition while the NAND gate 55 furnishes a clock signal, the plurality of capacitors 56 connected to the output of the NAND gate 55 become charged once the output of the NAND gate 55 makes a LOW to HIGH transition, and the plurality of capacitors 56 become discharged once the output of the NAND gate 55 makes a HIGH to LOW transition. As a result, a period of time that elapses from the output level of the NAND gate 55 starts changing until it reaches the threshold level of the NAND gate 55 is varied and the period of the clock signal is therefore varied. By applying the technique to the feedback loop of the prior art oscillation circuit 12 as shown in FIG. 11, the frequency of the multiplied clock signal can be adjusted finely.
The delay time adjustment by adjusting the capacitance connected to the output of the NAND gate 55 by controlling the signal level at one terminal of each of the plurality of capacitors 56 connected in parallel to the output of the NAND gate 55, however, results in a reduction in the speed of variations in signal level at the output of the NAND gate 55. Accordingly, the mixing of a noise into a signal generated by the feedback loop causes variations in the time at which the output of the NAND gate connected to the plurality of capacitors or delay element reaches its threshold voltage, resulting in an unstable oscillation frequency.
In case that the capacitance range of adjustment by controlling the signal level at one terminal of each of the plurality of capacitors 56 is limited to prevent the oscillation frequency from becoming unstable, the range of adjustment must become narrower so that the delay circuit is not adaptable to a wide range of frequency. Furthermore, such the limitation of the capacitance range of adjustment causes a problem that it is difficult to set the time delay caused by the delay circuit as shown in FIG. 15 to within a desired range due to variations in the ambient temperature and variations in the manufacturing process, in the worst case, the time delay cannot be adjusted.
Therefore, even though the above technique is implemented by using a digital delay line, it cannot take advantage of the benefits of the technique and causes a difficulty in making the oscillation frequency of the multiplied clock signal stable.